1. Field of the Invention
This invention relates generally to semiconductor devices. More particularly, the invention pertains to surface and external lead configurations of packaged semiconductor devices for electrical connection to other apparatus.
2. State of the Art
The continuing miniaturization of semiconductor devices is crucial to the electronics industry. Numerous improvements have contributed to the industry growth, including the development of leads-over-chip (LOC) assemblies and their inverse, chip-over-leads (COL) configurations. Thus, the die-attach support was eliminated and lead length was reduced, decreasing the package size. Further developments have included packaged devices in which a plurality of dice and leads therefor are encapsulated within a single package. Such is well illustrated, for example, in U.S. Pat. No. 5,331,235 of Chun, U.S. Pat. No. 5,471,369 of Honda et al., U.S. Pat. No. 5,483,024 of Russell et al., U.S. Pat. No. 5,498,902 of Hara, U.S. Pat. No. 5,508,565 of Hatakeyama et al., U.S. Pat. No. 5,530,292 of Waki et al., and U.S. Pat. No. 5,572,068 of Chun.
While such developments have filled a need, there remain applications wherein it is desirable to electrically attach separate, packaged semiconductor devices to each other, and to circuit boards, in combinations providing the desired results. This focuses our attention on the external electrical connections of the package by which it may be connected to other packaged devices, circuit boards, various electrical conduits, and a wide variety of electrical apparatuses.
The state of the art is illustrated by the representative prior art semiconductor devices shown in drawing FIGS. 1-4.
A representative example of a known packaged multi-chip semiconductor device 10 of the piggy-back type is shown in drawing FIGS. 1 and 2. A leads-over-chip (LOC) type construction with a small-outline-J-lead (SOJ) type package is depicted. The device includes a semiconductor chip or die 12 partially overcovered with an insulating layer(s) 14 such as polyimide. The die 12 includes a plurality of pads 16, each of which is electrically connected to a wire 18 whose opposite end is electrically connected to an end of an inner lead 20 of a leadframe. The die 12, insulative layers 14, wires 18, and inner leads 20 are enclosed in plastic 22, typically by a transfer molding process.
As shown in drawing FIG. 2, several packaged devices 10 of drawing FIG. 1 may be stacked with their outer leads 24 connected by, e.g., soldering to form a multi-chip package 26. As indicated, device 10B is superposed on device 10A and corresponding outer leads 24A and 24B of the devices are joined by soldering to provide a piggy-back type of package 26. The end portions 28 of the outer leads 24B are joined to the outer leads 24A.
This type of construction has several disadvantages. First, the outer leads 24B of the superposed device 10B must be bent differently from outer leads 24A of the underlying device 10A. Thus, the devices 10A and 10B cannot be interchanged, and the outer leads 24B of device 10B are not configured for attachment to a printed circuit board (PCB).
In addition, each device 10C, 10D (not shown) to be stacked atop device 10B requires a different outer lead configuration to enable proper joining of the stacked devices.
Turning now to drawing FIG. 3, a prior art semiconductor device 30 is depicted in which two dice 12C, 12D are combined, face-to-face, and joined to opposing sides of a single leadframe 32. The inner lead ends 34A which approach the electrical pads 16 from one side are positioned between the inner lead ends 34B which approach the pads 16 from the opposite side. Layers 38 of insulative material separate the dies 12C, 12D and leadframe 32 from each other generally. The combination of dice 12C, 12D and the attached leadframe 32 is encapsulated by plastic 22 within a single small-outline-J-lead (SOJ) package with conventional outer J-leads 36.
Drawing FIG. 4 illustrates a prior art semiconductor device 40 shown in U.S. Pat. No. 5,554,886 of Song. The device 40 may be vertically stacked in multiple units. A die 12 is wire-bonded to leads 42 of a leadframe 32. The inner portions of leads 42 are configured to have metal laminates 43 joined thereto, wherein surface portions 44 of the laminates are coplanar with a first major surface 46 of the plastic package 48 and are meant to comprise bond areas for solder bonding to additional packages. The outer portions of leads 36 have ends 52 which are formed to be parallel to the second major surface 50, opposite to first major surface 46. Each lead end 52 has a surface 54 for bonding to a circuit board or another device package. Thus, multiple units of the device 40 may be stacked and have corresponding surface portions 44 and 54 joined by solder.
Although the state of the art in package configuration is continually improving, ever-increasing demands for further miniaturization, circuit complexity, production speed, reduced cost, product uniformity and reliability require further improvements in semiconductor device connections by which the devices are readily electrically connected to circuit boards, electrical apparatus, and each other.
In particular, the need for a semiconductor device capable of electrical connection to a plurality of substrates, other devices, or various electrical apparatus in several configurations is presently needed.
In accordance with the invention, a package configuration for a semiconductor device is formed wherein the package size is reduced, stacking of packages is enabled without further modification of a lower or upper package, and the bonding of the device to electrical apparatuses is enhanced.
The external package configuration may be used with any internal configuration of dice, leads, insulative layers, heat sinks, die-to-lead connections, etc. Thus, the internal assembly configuration may comprise a Leads-Over-Chip (LOC), Chip-Over-Leads (COL), single or multiple die, wire bonded leads and/or tape-automated bonding (TAB), as well as other variations or combinations in construction.
A semiconductor package is formed in which the conductive lead has an intermediate portion which is encapsulated to have its exposed surface coplanar with the bottom surface of the package.
The outer lead is then an outward extension of the intermediate portion. The intermediate portion provides a bonding surface for joining to a circuit board, device, etc. In a further improvement of the invention, the encapsulant adjacent the edges of the intermediate lead portion is excised to a depth equaling about 0.1-1.0 of the lead thickness. The excised portion may take a variety of configurations.
In another improvement, the semiconductor device is formed with subsurface intermediate leads by which the leads of the apparatus being connected are properly positioned by chamfered sides.
In another improvement, a semiconductor package is formed with castellated sides and/or ends whereby the outer leads are bent upwardly to fit in the castellation grooves, while extending slightly from the grooves to provide bonding sites for electrical connection to other devices, etc. A mold assembly is described, infra, for producing the castellated package.